ANALOG PRODUCTS DIVISION

561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715

www.protekanalog.com

PA5331

Low Power 24-Bit, Stereo Audio CODEC

With Headphone Amplifier

95250 Rev.0. 01/10

NOT FOR USE IN LIFE SUPPORT SYSTEMS

MICRO-CONTROLLER CONFIGURATION INTERFACE

The device supports standard SPI and 2-wire micro-controller configuration interface. External micro-controller can completely

configure the device through writing to internal configuration registers. Please see section for the details of configuration register

definition.

The identical device pins are used to configure either SPI or 2-wire interface. In SPI mode, pin CE, CCLK and CDATA function as

SPI_CSn, SPI_CLK and SPI_DIN. In 2-wire mode, pin CE, CCLK and CDATA function as AD0, SCL and SDA. To select SPI mode,

apply high to low transition signal to CE pin. Otherwise the device will operate in 2-wire interface mode.

SPI

PA5331 has a SPI (Serial Peripheral Interface) compliant synchronous serial slave controller inside the chip. It provides the ability to

allow the external master SPI controller to access the internal registers, and thus control the operations of chip.

All lines on the SPI bus are unidirectional: The SPI_CLK is generated by the master controller and is primarily used to synchronize

data transfer, the SPI_DIN line carries data from the master to the slave; SPI_CSn is generated by the master to select PA5331.

The timing diagram of this interface is given in Figure 1. The high to low transition at SPI_CSn pin indicates the SPI interface

selected. Each write procedure contains 3 words, i.e. Chip Address plus R/W bit, internal register address and internal register data.

Every word length is fixed at 8 bits. The input SPI_DIN data are sampled at the rising edge of SPI_CLK clock. The MSB bit in each

word is transferred firstly. The transfer rate can be up to 10M bps.

Chip Address

7 bits - 0010000

0

SPI_DIN

SPI_CLK

SPI_CSn

1

R/

Wb

5

6

7

8

9

14

15

16

17

22

23

RAM

8 bits

Register Data

8 bits

RAM = Register Address Mapping

Figure 1 SPI Configuration Interface Timing Diagram

2-wire

2-wire interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The

timing diagram for data transfer of this interface is given in Figure 2. Data are transmitted synchronously to SCL clock on the SDA line

on a byte-by-byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred byte is

followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 100k bps.

Figure 2 Complete Data Transfer for 2-wire Interface

A master controller init

iates the transmission by sending a ―start‖ signal, which is defined as a high-to-low transition at SDA while SCL

is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be

001000x, where x equals AD0 (pin CE). The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received,

the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the

communication by generating a ―stop‖ signal, which is defined as a low-to-high transition at SDA while SCL is high.