AD9737ABBCZRL datasheet(5/64 Pages) AD

5 / 64 page

Data Sheet

AD9737A/AD9739A

Rev. | Page 5 of 64

LVDS DIGITAL SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-

1996 reduced range link, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1

Input Common-Mode Voltage Range, VCOM

825

1575

Logic High Differential Input Threshold, VIH_DTH

175

400

Logic Low Differential Input Threshold, VIL_DTH

−175

−400

Receiver Differential Input Impedance, RIN

120

Ω

Input Capacitance

1.2

LVDS Input Rate

1250

MSPS

LVDS Minimum Data Valid Period (tMDE) (See Figure 159)

344

LVDS CLOCK INPUT (DCI)2

Input Common-Mode Voltage Range, VCOM

825

1575

Logic High Differential Input Threshold, VIH_DTH

175

400

Logic Low Differential Input Threshold, VIL_DTH

−175

−400

Receiver Differential Input Impedance, RIN

120

Ω

Input Capacitance

1.2

Maximum Clock Rate

625

MHz

LVDS CLOCK OUTPUT (DCO)3

Output Voltage High (DCO_P or DCO_N)

1375

Output Voltage Low (DCO_P or DCO_N)

1025

Output Differential Voltage, |VOD|

150

200

250

Output Offset Voltage, VOS

1150

1250

Output Impedance, Single-Ended, RO

100

120

Ω

RO Single-Ended Mismatch

Maximum Clock Rate

625

MHz

DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.

DCI_P and DCI_N pins.

DCO_P and DCO_N pins with 100 Ω differential termination.

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