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LTC4252-2 Arkusz danych(PDF) 21 Page - Linear Technology

Numer części LTC4252-2
Szczegółowy opis  ??8V Hot Swap Controllers
PDF  34 Pages
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Producent  LINER [Linear Technology]
Strona internetowa  http://www.linear.com
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LTC4252-2 Arkusz danych(HTML) 21 Page - Linear Technology

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LTC4253/LTC4253A
21
425353afe
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the RSSCSS response.
An overconservative but simple approach begins with the
maximum circuit breaker current, given by:
I
CB(MAX) =
V
CB(MAX)
R
S
(14)
where VCB(MAX) is 60mV (55mV for the LTC4253A).
From the SOA curves of a prospective MOSFET, determine
the time allowed, tSOA(MAX). CSS is given by:
C
SS =
t
SOA(MAX)
0.916 • R
SS
for the LTC4253
C
SS =
t
SOA(MAX)
2.48 • R
SS
for the LTC4253A
(15)
In the above example, 60mV/40mΩ gives 1.5A. tSOA for
the IRF530S is 40ms. From Equation (15), CSS = 437nF.
Actual board evaluation showed that CSS = 100nF was ap-
propriate. The ratio ( RSS • CSS ) to tCL(CHARGE) is a good
gauge as large ratios may result in the time-out period
expiring prematurely. This gauge is determined empirically
with board level evaluation.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 3 for the LTC4253A. It was designed for
80W and CL = 100μF.
Calculate maximum load current: 80W/43V = 1.86A;
allowing for 83% converter efficiency, IIN(MAX) = 2.2A.
Calculate RS: from Equation (8) RS = 20mΩ.
Calculate ISHORT-CIRCUIT(MAX): from Equation (10)
ISHORTCIRCUIT(MAX) = 3.3A.
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
Calculate CT: from Equation (13) CT = 302nF. Select
CT  =  680nF, which gives the circuit breaker time-out
period tMAX = 5.9ms.
Consult MOSFET SOA curves: the IRF530S can handle 3.3A
at 100V for 8.3ms, so it is safe to use in this application.
Calculate CSS: using Equations (14) and (15) select
CSS = 33nF.
FREQUENCY COMPENSATION
The LTC4253 typical frequency compensation network
for the analog current limit loop is a series RC (10Ω)
and CC connected from GATE to VEE. Figure 6 depicts the
relationship between the compensation capacitor CC and
the MOSFET’s CISS. The line in Figure 6 is used to select
a starting value for CC based upon the MOSFET’s CISS
specification. Optimized values for CC are shown for sev-
eral popular MOSFETs. Differences in the optimized value
of CC versus the starting value are small. Nevertheless,
compensation values should be verified by board level
short-circuit testing.
As seen in Figure 5, at the onset of a short-circuit event,
the input supply voltage can ring dramatically due to series
inductance. If this voltage avalanches the MOSFET, current
continues to flow through the MOSFET to the output. The
analog current limit loop cannot control this current flow
and therefore the loop undershoots. This effect cannot be
eliminated by frequency compensation. A Zener diode is
required to clamp the input supply voltage and prevent
MOSFET avalanche.
Figure 6. Recommended Compensation
Capacitor CC vs MOSFET CISS for the LTC4253
MOSFET CISS (pF)
4253 F06
60
50
40
30
20
10
0
0
2000
4000
6000
8000
IRF530
IRF540
IRF740
IRF3710
NTY100N10
APPLICATIONS INFORMATION



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