CY2DP818ZXC datasheet(3/13 Pages) CYPRESS

3 / 13 page

CY2DP818

Document Number: 38-07061 Rev. *D

Page 3 of 13

Pin Configuration

Figure 1. 38-pin TSSOP pinout

GND

VDD

Q1A

Q1B

Q2A

Q2B

Q3A

Q3B

Q4B

Q5A

Q5B

Q6A

Q6B

Q7A

Q7B

Q8A

Q8B

GND

Q4A

GND

VDD

GND

VDD

InConfig

INPUT A

INPUT B

GND

VDD

Pin Description

Number

Pin Name

Type

Description

1, 9, 12, 18,

19, 20, 38

GND

POWER

Ground

2, 3, 4, 5, 6,

8, 13, 14,

15, 16, 17,

VDD

POWER

Power Supply

10, 11

Input A,

Input B

Default: LVPECL/LDVS

Optional: LVTTL/LVCMOS single pin

Clock Input. Either differential LVPECL/LVDS or single-ended

LVTTL/LVCMOS, as determined by InConfig. See Table 1 and

Table 2 for details.

37, 36, 35,

34, 33, 32,

31, 30, 28,

27, 26, 25,

24, 23, 22,

Q1(A,B),

Q2(A,B),

Q3(A,B),

Q4(A,B),

Q5(A,B),

Q6(A,B),

Q7(A,B),

Q8(A,B)

LVPECL

Differential Output Clocks

InConfig

LVTTL/LVCMOS

Control Input. Selects input type: either differential

LVPECL/LVDS or single-ended LVTTL/LVCMOS. See Table 1

and Table 2 for details.

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