SL4516B

System Logic

Semiconductor

SLS

Presettable Up/Down Counter

High-Voltage Silicon-Gate CMOS

The SL4516B Presettable Binary Up/Down Counter consists of four

synchronously clocked D-type flip-flops (with a gating structure to

provide T-type flip-flop capability) connected as counters. This

counter can be cleared by a high level on the RESET line, and can be

preset to any binary number present on the jam inputs by a high level

on the PRESET ENABLE line.

If the CARRY-IN input is held low, the counter advances up or

down on each positive-going clock transition. Synchronous cascading

is accomplished by connecting all clock inputs in parallel and

connecting the CARRY-OUT of a less significant stage to the CARRY-

IN of a more significant stage.

The SL4516B can be cascaded in the ripple mode by connecting the

CARRY-OUT to the clock of the next stage. If the UP/DOWN input

changes during a terminal count, the CARRY-OUT must be gated with

the clock, and the UP/DOWN input must change while the clock

is high. This method provides a clean clock signal to the

subsequent counting stage.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25

°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

ORDERING INFORMATION

SL4516BN Plastic

SL4516BD SOIC

° to 125° C for all packages

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Outputs

CL

CI

U/D

PE

R

Mode

X

H

X

L

L

NO COUNT

L

H

L

L

COUNT UP

L

L

L

L

COUNT

DOWN

X

X

X

H

L

PRESET

X

X

X

X

H

RESET

X = don’t care

LOGIC DIAGRAM

PIN 8= GND