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L6472PDTR Arkusz danych(PDF) 18 Page - STMicroelectronics |
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L6472PDTR Arkusz danych(HTML) 18 Page - STMicroelectronics |
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18 / 69 page ![]() Pin connection L6472 18/69 Doc ID 022729 Rev 1 3 STBY\RST Logic input Standby and reset pin. LOW logic level resets the logic and puts the device into standby mode. If not used, it should be connected to VDD 25 STCK Logic input Step-clock input EPAD Exposed pad Ground Internally connected to PGND, AGND and DGND pins Table 6. Pin description (continued) No. Name Type Function |
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