Obsolete

Product(s)

- Obsolete

Product(s)

STA020

8/14

RST and CBL (TRNPT is low)

When RST goes low, the differential line drivers are set to ground. In order to properly synchronize the

ST020 to the audio serial port, the transmit timing counters, which include CBL, are not enabled after RST

goes high until eight and one half SCK periods after reset is exited) of FSYNC. When FSYNC is configured

as a left/right signal (all defined formats except 2), the counters and CBL are not enabled until the right

sample is being transmitted). This guarantees that channel A is left and channel B is right as per the digital

audio interface specs.

As shown in Figure 4, channel block start output (CBL), can assist in serially inputting the C, U and V bits

as CBL goes high one bit period before the first bit of the preamble of the first sub-frame of the channel

status block is transmitted. This sub-frame contains channel status byte 0, bit 0. CBL returns low one bit

period before the start of the frame that contains bit 0 of channel status byte 16. CBL is not available when

the CD subcode port is enabled.

Figure 4 illustrates timing for stereo data input on the audio port. Notice how CBL rises while the right

channel data (Right 0) is input, but the previous left channel (Left 0) is being transmitted as the first sub-

frame of the channel status block (starting with preamble Z). The C, U, and V input ports only need to be

valid for a short period after FSYNC changes. A sub-frame includes one audio sample while a frame in-

cludes a stereo pair. A channel status (C.S.) block contains 24 bytes of channel status and 384 audio sam-

ples (or 192 stereo pairs, or frames, of samples). Figure 4 shows the CUV ports as having left and right

bits (e.g. CUV0L, CUV0R). Since the C.S. block is defined as 192 bits, or one bit per frame, there are ac-

tually 2 C.S. blocks, one for channel A (left) and one for channel B (right). When inputting stereo audio

data, both blocks normally contain the same information, so C0L and C0R from the input port pin are both

channel status bit 0 of byte 0, which is defined as professional/consumer. These first two bits from the

port, C0L and C0R, are logically OR’ed with the inverse PRO, since PRO is a dedicated channel status

pin defined as C.S. bit 0.

Also, if in professional mode, C1, C6, C7 and C9 are dedicated C.S. pins. The inverse of C1 is logically

OR’ed with channel status input ports bits C1L and C1R. In similar fashion, C6, C7 and C9 are OR’ed with

their respective input bits. Also, the C bits in CUV128L and CUV128R are both channel status block bit

128, which is bit 0 of channel status byte 16.

Figure 4. CBL and Transmitter Timing.

CUV0L

CUV191R

CUV0R

CUV0L

CUV1L

CUV0R

CUV1R

CUV1L

CUV128R

CUV128L

CUV0L

CUV191R

CUV0R

CUV0L

LEFT 0

RIGHT 0

LEFT 1

LEFT 128

RIGHT 128

LEFT 0

RIGHT 0

C BITS FROM CPIN

C BITS OR'ed

w/PRO pin

C BITS OR'ed

w/C1 pin

BITS 0 of C.S.

BLOCK BYTE 16

RIGHT 191

LEFT 0

RIGHT 0

LEFT

128

RIGHT

128

Preamble Y

VUCP191R

Preamble Z

VUCP0L

Preamble Y

VUCP0R

VUCP127R

Preamble X

VUCP128L

Preamble Y

Preamble Z

Aux Data

LSB

Left 0 - Audio Data

MSB V0 U0 C0 P0

28 29 30 31

27

8

37

4

0

SUB-FRAME

bit

D99AU990

SDATA

TRNPT high

CBL

TRNPT low

FSYNC

C,U,V

TRNPT high

TRNPT low

TXP

TXN