STA369BWS datasheet(31/89 Pages) STMICROELECTRONICS

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STA369BWS

Doc ID 16861 Rev 4

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Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers maps each I2S input channel to its corresponding processing channel.

6.1.3

Configuration register C (addr 0x02)

FFX power output mode

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

FFX compensating pulse size register

Table 21.

Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

C1IM

0: processing channel 1 receives left I2S Input

1: processing channel 1 receives right I2S Input

7R/W

C2IM

0: processing channel 2 receives left I2S Input

1: processing channel 2 receives right I2S Input

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

011

Table 22.

FFX power output mode

Bit

R/W

RST

Name

Description

R/W

OM0

Selects configuration of FFX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

1R/W

OM1

Table 23.

FFX compensating pulse size bits

Bit

R/W

RST

Name

Description

2R/W

CSZ0

When OM[1,0] = 11, this register determines the

size of the FFX compensating pulse from 0 clock

ticks to 15 clock periods.

3R/W

CSZ1

4R/W

CSZ2

5R/W

CSZ3

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