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TS4621ML Arkusz danych(PDF) 30 Page - STMicroelectronics |
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TS4621ML Arkusz danych(HTML) 30 Page - STMicroelectronics |
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30 / 40 page ![]() Application information TS4621ML 30/40 Doc ID 023181 Rev 1 Figure 67. Typical application schematic with IEC 61000-4-2 ESD protection By adding this ESD protection, the TS4621ML complies with the IEC 61000-4-2 level 4 standard on jack pins. Our demonstration board has been tested using the same conditions as those outlined in the IEC 61000-4-2 standard. Results may differ depending on the layout of the PCB. ● 15 kV (air discharge) ● 8 kV (contact discharge) This IPAD has an internal series resistor Rout =15 Ω +/-20 % and an output capacitor Cout =3.2 nF +/-25%. 4.3.7 Integrated input low-pass filter The TS4621ML has an integrated internal first-order low-pass filter with a -3 dB cutoff . This integrated filter is present on each input and filters any out-of-band audio noise coming from the audio source. 4.4 Single-ended input configuration The TS4621ML can be used in a single-ended input configuration. InR- and InL- or InR+ and InL+ can be shorted to ground through input capacitors. All Cin capacitors must have the same value to keep the same PSRR performance as in a differential input configuration. Figure 68 and Figure 69 show how to connect the TS4621ML. Note the ground connection of each input. To avoid PSRR issues resulting from any ground noise, this connection must be done on the ground of the audio source and not on the ground of the TS4621ML itself. 1 2 3 J1 Cin 1 µF Cin 1 µF Cin 1 µF Cin 1 µF C12 2.2 µF Cs 2.2 µF Css 2.2 µF Ct 10 µF L1 3.3 µH Vbat Positive left input Positive right input + - + - Negative supply Positive Supply AGnd C1 C2 AVdd InL- InL+ InR+ InR- VoutL VoutR CMS Level detector Level detector Sw HpVdd PVss Negative right input Negative left input A1 2 C 1 C A2 B2 Gnd IPad AM06151 |
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