SPC560P60L3 datasheet(23/104 Pages) STMICROELECTRONICS

23 / 104 page

SPC56xP54x, SPC56xP60x

Introduction

Doc ID 18340 Rev 3

23/104

1.5.24

Analog-to-digital converter (ADC)

The ADC module provides the following features:

Analog part:

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1 on-chip analog-to-digital converter

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10-bit AD resolution

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1 sample and hold unit per ADC

●

Conversion time, including sampling time, less than 1

s (at full precision)

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Typical sampling time is 150 ns min. (at full precision)

●

Differential non-linearity error (DNL) ±1 LSB

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Integral non-linearity error (INL) ±1.5 LSB

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Total unadjusted error (TUE) <3 LSB

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Single-ended input signal range from 0 to 3.3 V / 5.0 V

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ADC and its reference can be supplied with a voltage independent from VDDIO

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ADC supply can be equal or higher than VDDIO

●

ADC supply and the ADC reference are not independent from each other (they are

internally bonded to the same pad)

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Sample times of 2 (default), 8, 64, or 128 ADC clock cycles

Digital part:

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27 input channels (26 + 1 internally connected)

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4 analog watchdogs to compare ADC results against predefined levels (low, high,

range) before results are stored

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2 operating modes: Normal mode and CTU control mode

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Normal mode features

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ADC state machine managing 3 request flows: regular command, hardware

injected command, and software injected command

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Selectable priority between software and hardware injected commands

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DMA compatible interface

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CTU control mode features

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Triggered mode only

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4 independent result queues (2 × 16 entries, 2 × 4 entries)

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Result alignment circuitry (left justified; right justified)

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32-bit read mode allows to have channel ID on one of the 16-bit part

–

DMA compatible interfaces

1.5.25

Cross triggering unit (CTU)

The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests

on user selected conditions with minimized CPU load for dynamic configuration.

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