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SPEAR320 Arkusz danych(PDF) 51 Page - STMicroelectronics |
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SPEAR320 Arkusz danych(HTML) 51 Page - STMicroelectronics |
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51 / 73 page ![]() SPEAr320 Timing requirements Doc ID 16755 Rev 5 51/73 7.3.1 DDR2 read cycle timings Figure 6. DDR2 read cycle waveforms 7.3.2 DDR2 write cycle timings Figure 7. DDR2 write cycle waveforms Table 29. DDR2 read cycle timings Symbol Description Min Max Unit tCK DDR_MEM_CLKP/CLKN cycle time 3 ns tDQSQ DQS to DQ input setup time 0 0.25tCK+0.4 ns tQH DQS to DQ input hold time 0.25tCK+0.7 0.5tCK ns tDQSQ tQH tQH tDQSQ tDQSQ DDR_MEM_DQS DDR_MEM_DQ DDR_MEM_CLKP/ DDR_MEM_CLKN tCK DDR_MEM_DQS DDR_MEM_DQ DDR_MEM_CLKP/ DDR_MEM_CLKN tDS tDH tDH tDS tDS tDH tDQSS |
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