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HT32F1253 Arkusz danych(PDF) 12 Page - Holtek Semiconductor Inc |
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HT32F1253 Arkusz danych(HTML) 12 Page - Holtek Semiconductor Inc |
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12 / 35 page ![]() Rev. 1.10 1� of �5 ���i� 1�� �01� ��-bit �RM Co�tex™-M� MCU HT��F1�51/51B/5�/5� Inter-integrated Circuit (I2C) ▀ Support both master and slave mode with a frequency of up to 400 kHz ▀ Provide arbitration function ▀ Supports 7-bit and 10-bit addressing mode and general call addressing The I2C Module is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module provides two data transfer rates: (1) 100 kHz in the Standard mode or (2) 400 kHz in the Fast mode. The SCL period generation register is used to setup different kinds of duty cycle implementation for the SCL pulse. The SDA line which is connected to the whole I2C bus is a bi-directional data line between the master and slave devices used for the transmission and reception of data. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. Serial Peripheral Interface (SPI) ▀ SPI interfaces with a frequency of up to 18 MHz ▀ Support both master and slave mode ▀ FIFO Depth: 8 levels ▀ Multi-master and multi-slave operation The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function in both master and slave mode. The SPI interface uses 4 pins, among which are the serial data input and output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device acts as a master which controls the data flow using the SEL and SCK signals to indicate the start of the data communication and the data sampling rate. To receive a data byte, the streamed data bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data transmission is carried in a similar way but with a reverse sequence. The mode fault detection provides a capability for multi-master applications. |
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