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CXR702F080 Arkusz danych(PDF) 21 Page - Sony Corporation |
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CXR702F080 Arkusz danych(HTML) 21 Page - Sony Corporation |
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21 / 32 page ![]() – 21 – CXR702F080 Pin Circuit format After a reset IP CMOS Schmitt input Internal reset signal RSTWD (from watchdog timer) TDI, TMS, TCK (to CPU core) IP TRST (to CPU core) IP RTCK TDO TDO output enable TEST0, TEST1 (to test circuit) IP TEST2 (to test circuit) IP RST Pull-up TDI TMS TCK Pull-up TRST Pull-down RTCK High TDO Low TEST0 TEST1 Hi-Z TEST2 Pull-down PWE IP Hi-Z PWE |
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