WM8728

Production Data

w

PD, Rev 4.6 August 2008

21

REGISTER MAP

WM8728 uses a total of 4 program registers, which are 16-bits long. These registers are all loaded through input pin SDIDEM.

Using either 2-wire or 3-wire serial control mode as shown Figure 8 and Figure 9

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

M0

0

0

0

0

0

0

0

UPDATEL

LAT7

LAT6

LAT5

LAT4

LAT3

LAT2

LAT1

LAT0

M1

0

0

0

0

0

0

1

UPDATER RAT7

RAT6

RAT5

RAT4

RAT3

RAT2

RAT1

RAT0

M2

0

0

0

0

0

1

0

0

0

0

IW2

IW1

IW0

PWDN DEEMPH

MUT

M3

0

0

0

0

0

1

1

IZD

0

0

BCP

REV

0

ATC

LRP

I

ADDRESS

DATA

Table 7 Mapping of Program Registers

REGISTER

ADDRESS

(A3,A2,A1,A0)

BITS

NAME

DEFAULT

DESCRIPTION

[7:0]

LAT[7:0]

11111111 (0dB)

Attenuation data for left channel in 0.5dB steps, see Table 10

0000

DACL

Attenuation

8

UPDATEL

0

Attenuation data load control for left channel.

0: Store DACL in intermediate latch (no change to output)

1: Store DACL and update attenuation on both channels.

[7:0]

RAT[7:0] 11111111 (0dB)

Attenuation data for right channel in 0.5dB steps, see Table 10

0001

DACR

Attenuation

8

UPDATER

0

Attenuation data load control for right channel.

0: Store DACR in intermediate latch (no change to output)

1: Store DACR and update attenuation on both channels.

0

MUT

0

Left and right DACs soft mute control.

0: No mute

1: Mute

1

DEEMPH

0

De-emphasis control.

0: De-emphasis off

1: De-emphasis on

2

PWDN

0

Left and Right DACs Power-down Control

0: All DACs running, output is active

1: All DACs in power saving mode, output muted

0010

DAC Control

[5:3]

IW[2:0]

0

Audio data format select, see Table 15

0

0

Audio data format select, see Table 15

1

LRP

0

Polarity select for LRCIN/DSP mode select.

0: normal LRCIN polarity/DSP late mode

1: inverted LRCIN polarity/DSP early mode

2

ATC

0

Attenuator Control.

0: All DACs use attenuation as programmed.

1: Right channel DACs use corresponding left DAC

attenuation

4

REV

0

Output phase reverse.

5

BCP

0

BCKIN Polarity

0 : normal BCKIN polarity

1: inverted BCKIN polarity

0011

Interface

Control

8

IZD

0

Infinite ZERO detection circuit control and automute control

0: Infinite ZERO detect disabled

1: Infinite ZERO detect enabled

Table 8 Register Bit Descriptions