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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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WM8945ECS/R Arkusz danych(PDF) 18 Page - Wolfson Microelectronics plc |
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WM8945ECS/R Arkusz danych(HTML) 18 Page - Wolfson Microelectronics plc |
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18 / 169 page  WM8945 Production Data w PD, May 2011, Rev 4.1 18 SLAVE MODE BCLK (input) LRCLK (input) ADCDAT (output) DACDAT (input) tDS tDD tDH tLRH tLRSU tBCH tBCL tBCY Figure 4 Audio Interface Timing – Slave Mode Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25 oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing – Slave Mode BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 20 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 20 ns DACDAT set-up time to BCLK rising edge tDS 20 ns Note: BCLK period must always be greater than or equal to MCLK period. |
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