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WM8978CGEFL/V Arkusz danych(PDF) 43 Page - Wolfson Microelectronics plc |
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WM8978CGEFL/V Arkusz danych(HTML) 43 Page - Wolfson Microelectronics plc |
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43 / 118 page ![]() Production Data WM8978 w PD, Rev 4.5, October 2011 43 ALC HOLD TIME (NORMAL MODE ONLY) In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins its decay phase (gain increasing). The hold time is set by the ALCHLD register. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R33 ALC Control 2 7:4 ALCHLD 0000 ALC hold time before gain is increased. Table 23 ALC Hold Time If the hold time is exceeded this indicates that the signal has reached a new average level and the ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold during the hold period, the hold phase is abandoned and the ALC returns to normal operation. Figure 20 ALCLVL |
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