WM8351CGEBSLASHV datasheet(57/330 Pages) WOLFSON

57 / 330 page

Production Data

WM8351

PD, April 2012, Rev 4.5

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

111 = Reserved

7:4

FLL_RSP_RAT

0000

FLL Loop Gain

0000 = x 1 (Recommended value)

0001 = x 2

0010 = x 4

0011 = x 8

0100 = x 16

0101 = x 32

0110 = x 64

0111 = x 128

1000 = x 256

Recommended that these are not

changed from default.

2:0

FLL_RATE

[2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended value)

001 = FVCO / 2

010 = FVCO / 4

011 = FVCO / 8

100 = FVCO / 16

101 = FVCO / 32

Recommended that these are not

changed from default.

R43 (2Bh)

FLL Control

15:11

FLL_RATIO

[4:0]

(0Eh)

CLK_VCO is divided by this integer, valid

from 1 .. 31.

1 recommended for high freq reference

8 recommended for low freq reference

9:0

FLL_N [9:0]

086h

FLL integer multiplier N for CLK_REF

R44 (2Ch)

FLL Control

15:0

FLL_K [15:0]

C226h

FLL fractional multiplier K for CLK_REF.

This is only used if FLL_FRAC is set.

R45 (2Dh)

FLL Control

FLL_REF_FRE

Low frequency reference locking

0 = High frequency reference locking

(recommended for reference clock >

48kHz)

1 = Lock frequency reference locking

(recommended for reference clock <=

48kHz)

FLL_FRAC

Fractional enable

0 = Integer Mode

1 = Fractional Mode

1 recommended in all cases

1:0

FLL_CLK_SRC

[1:0]

Select FLL input clock Source

00 = MCLK

01 = DACLRCLK

10 = ADCLRCLK

11 = CLK_32K_REF

Table 17 FLL Control Registers

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