RT9108NL datasheet(12/13 Pages) RICHTEK

12 / 13 page

RT9108NL

DS9108NL-01

June 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Layout Considerations

For the best performance of the RT9108NL, the below

PCB Layout guidelines must be strictly followed.

Place the decoupling capacitors as close as possible

to the AVCC, PVCCL, PVCCR and GND pins. For

achieving a good quality, consider adding a small, good

performance low ESR ceramic capacitor between 220

pF and 1000pF and a larger mid-frequency capacitor

between 0.1

μF and 1μF to the PVCC pins of the chip.

Do not trace out the NC pins (Pin13, 16 and Pin27) to

avoid the pin short issue.

FAULT

LINP

LINN

PGND

OUTPL

BSPL

PVCCL

GAIN0

GAIN1

OUTNL

AVCC

AGND

GVDD

PLIMIT

RINN

RINP

OUTPR

PGND

OUTNR

BSNL

BSPR

BSNR

MUTE

PVCCR

AGND

PVCC

CIN

Audio

Input

CIN

Audio

Input

GND

The decoupling

capacitor (CS)

must be placed

as close to the

IC as possible

GND

Do not

trace out

The decoupling

capacitor (CS)

must be placed

as close to the

IC as possible

Do not

trace out

The decoupling

capacitor (CS)

must be placed

as close to the

IC as possible

Figure 4. PCB Layout Guide

Keep the differential output traces as wide and short as

possible.

The traces of (LINP & LINN, RINP & RINN) and (OUTPL

& OUTNL, OUTPR & OUTNR) should be kept equal width

and length respectively.

The thermal pad must be soldered to the PCB for proper

thermal performance and optimal reliability. The

dimensions of the thermal pad and thermal land should

be larger for application. The vias should connect to a

solid copper plane, either on an internal layer or on the

bottom layer of the PCB.

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