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AD2S90AP Arkusz danych(PDF) 3 Page - Analog Devices

Numer części AD2S90AP
Szczegółowy opis  Low Cost, Complete 12-Bit Resolver-to-Digital Converter
PDF  12 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD2S90AP Arkusz danych(HTML) 3 Page - Analog Devices

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AD2S90
REV. D
–3–
AD2S90
Parameter
Min
Max
Units
Test Conditions/Notes
tDIR
200
ns
DIR to CLKOUT Positive Edge
tCLK
250
400
ns
CLKOUT Pulsewidth
tABN
250
ns
CLKOUT Negative Edge to A, B and NM Transition
Parameter
AD2S90
Units
Test Conditions/Notes
t1
150
ns max
CS to DATA Enable
t2
1
600
ns min
CS to 1st SCLK Negative Edge
t3
250
ns min
SCLK Low Pulse
t4
250
ns min
SCLK High Pulse
t5
100
ns max
SCLK Negative Edge to DATA Valid
t6
600
ns min
CS High Pulsewidth
t7
150
ns max
CS High to DATA High Z (Bus Relinquish)
NOTE
1SCLK can only be applied after t
2 has elapsed.
(VDD = +5 V
5%, VSS = –5 V
5%, AGND = DGND = 0 V, TA = –40 C to +85 C unless
otherwise noted)
TIMING CHARACTERISTICS1, 2
LSB
MSB
t3
t4
t5
t1
t7
t6
t*
t2
*THE MINIMUM ACCESS TIME: USER DEPENDENT
CSB
SCLK
DATA
Figure 1. Serial Interface
NOTES
1Timing data are not 100% production tested. Sample tested at +25
°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using
10 pF, 100 k
Ω load.
2Capacitance of data pin in high impedance state = 15 pF.
A
B
90
180
NM
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
360
Figure 2. Incremental Encoder
CLKOUT
A, B, NM
DIR
COUNTER IS CLOCKED
ON THIS EDGE
tDIR
tABN
tCLK
Figure 3. DIR/CLKOUT/A, B and NM Timing



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