AD6622SSLASHPCB datasheet(6/28 Pages) AD

6 / 28 page

AD6622

–6–

REV. 0

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK.

2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1

3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER

VERSUS A RAM REGISTER.

4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.

W (WR)

DS (RD)

A[2:0]

D[7:0]

DTACK

(RDY)

tHRW

tSAM

tHAM

tSAM

tHAM

tACC

VALID ADDRESS

VALID DATA

tDDTACK

tHDS

Figure 7. MNM Microport Write Timing Requirements

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK.

2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1

3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER

VERSUS A RAM REGISTER.

4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.

W (WR)

DS (RD)

A[2:0]

D[7:0]

DTACK

(RDY)

tSAM

tACC

VALID ADDRESS

tZD

VALID DATA

tDD

tHA

tZD

tHDS

tDDTACK

Figure 8. MNM Microport Read Timing Requirements

AD6622S/PCB Arkusz danych(PDF) 6 Page - Analog Devices

AD6622S/PCB Arkusz danych(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Arkusz danych Pobierz

Link URL