AD8320ARP datasheet(3/20 Pages) AD

3 / 20 page

AD8320

–3–

REV. 0

LOGIC INPUTS (TTL/CMOS Logic)

Parameter

Min

Typ

Max

Units

Logic “1” Voltage

2.1

5.0

Logic “0” Voltage

0.8

Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN

020

Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN

–450

–75

Logic “1” Current (VINH = 5 V) PD

190

µA

Logic “0” Current (VINL = 0 V) PD

–320

–70

µA

TIMING REQUIREMENTS

Parameter

Min

Typ

Max

Units

Clock Pulse Width (TWH)

12.0

Clock Period (TC)

32.0

Setup Time SDATA vs. Clock (TDS)

6.5

Setup Time

DATEN vs. Clock (T

ES)

17.0

Hold Time SDATA vs. Clock (TDH)

5.0

Hold Time

DATEN vs. Clock (T

EH)

3.0

Input Rise and Fall Times, SDATA,

DATEN, Clock (T

R, TF)10

TES

VALID DATA WORD G1

MSB. . . .LSB

GAIN TRANSFER (G1)

TDS

TEH

8 CLOCK CYCLES

GAIN TRANSFER (G2)

TOFF

TGS

ANALOG

OUTPUT

SIGNAL AMPLITUDE (p-p)

PEDESTAL

CLK

SDATA

DATEN

TON

TWH

VALID DATA WORD G2

Figure 2. Serial Interface Timing

VALID DATA BIT

MSB

MSB-1

MSB-2

TDS

TDH

CLK

Figure 3.

(

DATEN, CLK, SDATA, 5 V

≤ V

≤ 12 V; Full Temperature Range)

(Full Temperature Range, VCC Supply Range, TR = TF = 4 ns, FCLK = 8 MHz unless otherwise noted.)

AD8320ARP Arkusz danych(PDF) 3 Page - Analog Devices

AD8320ARP Arkusz danych(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Arkusz danych Pobierz

Link URL