EM47FM0888MBA

Jul. 2012

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DLL Enable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 =

0), the DLL is automatically disabled when entering self-refresh operation and is automatically re-enabled upon

exit of self-refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must

occur before a read or synchronous ODT command can be issued to allow time for the internal clock to be

synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the

tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM

does not require DLL for any Write operation, except when RTT_WR is enabled and the DLL is required for

proper ODT operation. For more detailed information on DLL Disable operation refers to “DLL-off Mode”.

The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be

disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2}

to {0,0,0} via a mode register set command during DLL-off mode. The dynamic ODT feature is not supported at

DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT

externally.

ODT Rtt Values

DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal

termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2 to

enable a unique RTT value when ODT is enabled during writes. The Rtt_WR value can be applied during writes

even when Rtt_Nom is disabled.

Additive Latency

Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable

bandwidths in DDR3 SDRAM. In this operation, It allows a read or write command (either with or without

auto-precharge) to be issued immediately after the active command. The command is held for the time of the

Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of

the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS

Write Latency (CWL) register settings.