REV. 0

–6–

AD8600

TRANSFER EQUATIONS

Output Voltage

O

V

REF

256

where i is the DAC channel number and D is the decimal value

of the DAC register data.

Table I. Truth Table

EN

R/W

CS LD

RS

Operation

Write to DAC Register

–

X

H

L

H

Update DAC Register

L

X

H

–

H

Update DAC Register

+

X

H

L

H

Latches DAC Register

L

X

H

+

H

Latches DAC Register

L

L

L

L

H

DAC Register Transparent

Write to Input Register

L

L

L

H

H

Load Data to Input Register at

Decoded Address

+

L

L

H

H

Latches Data in Input Register at

Decoded Address

L

L

+

H

H

Latches Data in Input Register at

Decoded Address

Readback Input Registers

X

H

L

H

H

Input Register Readback (Data

Access)

X

H

+

H

H

Hi-Z Readback Disconnects from

Bus

X

X

H

X

X

Hi-Z on Data Bus

Reset

X

X

X

X

L

Clear All Registers to Zero,

X

X

H

H

+

Latches All Registers to Zero

LX

LH

+

CS

= Low; Input Register Ready

for R/W, DAC Register Latched

to Zero

NOTES

Decoded DAC Register

O

where A is the decimal value of the decoded address bits A3,

A2, A1, A0 (LSB).

Address, CS, R/W and data inputs should be stable prior to acti-

vation of the active low EN input. Input registers are transpar-

ent when EN is low. When EN returns high, data is latched into

the decoded input register. When the load strobe LD and EN

pins are active low, all input register data is transferred to the

DAC registers. The DAC registers are transparent while they

are enabled.

Table II. Address Decode Table

A3

A2

A1

A0

Addr

DAC

(MSB)

(LSB)

Code

Updated

(Binary)

(Hex)

000

0

0

O0

000

1

1

O1

001

0

2

O2

001

1

3

O3

010

0

4

O4

010

1

5

O5

011

0

6

O6

011

1

7

O7

100

0

8

O8

100

1

9

O9

101

0

A

O10

101

1

B

O11

110

0

C

O12

110

1

D

O13

111

0

E

O14

111

1

F

O15