AD9772AST datasheet(24/30 Pages) AD

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AD9772

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AD9772 EVALUATION BOARD

The AD9772-EB is an evaluation board for the AD9772 TxDAC.

Careful attention to layout and circuit design, combined with

prototyping area, allows the user to easily and effectively evalu-

ate the AD9772 in different modes of operation.

Referring to Figures 54 and 55, the AD9772’s performance can

be evaluated differentially or single-ended using a transformer,

differential amplifier, or directly coupled output. To evaluate

the output differentially using the transformer, remove jumpers

JP12 and JP13 and monitor the output at J6 (IOUT). To evalu-

ate the output differentially, remove the transformer (T2) and

install jumpers JP12 and JP13. The output of the amplifier can

be evaluated at J13 (AMPOUT). To evaluate the AD9772

single-ended and directly coupled, remove the transformer and

jumpers (JP12 and JP13) and install resistors R16 or R17 with

Ω.

The digital data to the AD9772 comes across a ribbon cable

which interfaces to a 40-pin IDC connector. Proper termina-

tion or voltage scaling can be accomplished by installing RN2

and/or RN3 SIP resistor networks. The 22

Ω DIP resistor net-

work, RN1, must be installed and helps reduce the digital data

edge rates. A single-ended CLOCK input can be supplied via

the ribbon cable by installing JP8 or more preferably via the

SMA connector, J3 (CLOCK). If the CLOCK is supplied by J3,

the AD9772 can be configured for a differential clock interface

by installing jumpers JP1 and configuring JP2, JP3, and JP9 for

the DF position. To configure the AD9772 clock input for a

single-ended clock interface, remove JP1 and configure JP2, JP3

and JP9 for the SE position.

The AD9772’s PLL clock multiplier can be disabled by config-

uring jumper JP5 for the L position. In this case, the user must

supply a clock input at twice (2

× )the data rate via J3 (CLOCK).

The 1

× clock is made available on SMA connector, J1

(PLLLOCK) and should be used to trigger a pattern generator

directly or via a programmable pulse generator. Note, PLLLOCK

is capable of providing a 0 V to 0.85 V output into a 50

Ω load.

To enable the PLL clock multiplier, JP5 must be configured for

the H position. In this case, the clock may be supplied via the

ribbon cable (i.e., JP8 installed) or J3 (CLOCK). The divide-

by-N ratio can be set by configuring JP6 (DIV0) and JP7 (DIV1).

The AD9772 can be configured for Baseband or Direct IF Mode

operation by configuring jumpers JP11 (MOD0) and JP10

(MOD1). For baseband operation, JP10 and JP11 should be

configured in the L position. For direct IF operation, JP10 and

JP11 should be configured in the H position. For direct IF

operation without “zero-stuffing,” JP11 should be configured in

the H position while JP10 should be configured in the low position.

The AD9772’s voltage reference can be enabled or disabled via

JP4 (EXT REF IN). To enable the reference, configure JP in

the INT position. A voltage of approximately 1.2 V will appear

at the TP6 (REFIO) test point. To disable the internal refer-

ence, configure JP4 in the EXT position and drive TP6 with an

external voltage reference. Lastly, the AD9772 can be placed in

the SLEEP mode by driving the TP11 test point with logic level

HIGH input signal.

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