AD9834 datasheet(13/20 Pages) AD

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AD9834

–13–

REV PrM

PRELIMINARY TECHNICAL DATA

Table 8: Writing 3FFF to the 14 LSBs of FREQ1 REG

SDATA input

Result of input word

0000 0000 0000 0000

Control word write (D15, D14 = 00);

B28 (D13) = 0; HLB (D12) = 0, i.e. LSBs

1011 1111 1111 1111

FREQ1 REG write (D15, D14 = 10);

14 LSBs = 3FFF

Table 9: Writing 3FFF to the 14 MSBs of FREQ0 REG

SDATA input

Result of Input word

0001 0000 0000 0000

Control word write (D15, D14 = 00);

B28 (D13) = 0; HLB (D12) = 1, i.e. MSBs

0111 1111 1111 1111

FREQ0 REG write (D15, D14 = 01);

14 MSBs = 3FFF

Writing to a Phase Register:

When writing to a phase register, bits D15 and D14 are

set to 11. Bit D13 identifies which phase register is being

loaded.

Table 10. Phase Register Bits

D15 D14

D13

D12

D11

D 0

MSB

12 PHASE0 BITS

LSB

MSB

12 PHASE1 BITS

LSB

The RESET Function

The RESET function resets appropriate internal registers

to zero to provide an analog output of midscale. RESET

does not reset the phase, frequency or control registers.

When the AD9834 is powered up, the part should be re-

set. To reset the AD9834, set the RESET pin/bit to 1. To

take the part out of reset, set the pin/bit to 0. A signal will

appear at the DAC output 7 MCLK cycles after RESET is

set to 0.

The RESET function is controlled by both the RESET

pin and the RESET control bit. If the control bit PIN/SW

= 0, the RESET bit controls the function, whereas if PIN/

SW = 1, the pin control the function.

Table 11: Applying RESET

RESET pin

RESET bit

PIN/SW

Result

No Reset Applied

Internal Registers Reset

No Reset Applied

Internal Registers Reset

The effect of asserting the RESET pin is seen immedi-

ately at the output, i.e. the zero to one transition of this

pin is not sampled. However, the negative transition of

RESET is sampled on the internal falling edge of MCLK.

The Sleep Function

Sections of the AD9834 which are not in use can be pow-

ered down minimise power consumption. This is done

using the Sleep Function. The parts of the chip that can

be powered down are the Internal clock and the DAC.

The DAC can be powered down through hardware or

software. The pin/bits required for the Sleep Function are

outlined in Table 12.

Table 12: Applying the SLEEP Funct

ion

SLEEP

SLEEP1 SLEEP12

PIN/SW

Result

bit

No powerdown

DAC Powered Down

No powerdown

DAC Powered Down

Internal Clock disabled

Both the DAC powered

down and the Internal

Clock disabled

DAC Powered Down: This is useful when the AD9834 is

used to output the MSB of the DAC data only. In this

case, the DAC is not required so it can be powered down

to reduce power consumption.

Internal Clock disabled: When the internal clock of the

AD9834 is disabled the DAC output will remain at its

present value as the NCO is no longer accumulating. New

frequency, phase and control words can be written to the

part when the SLEEP1 control bit is active. The

synchronising clock is still active which means that the

selected frequency and phase registers can also be changed

either at the pins or by using the control bits. Setting the

SLEEP1 bit equal to 0 enables the MCLK. Any changes

made to the registers while SLEEP1 was active will be

seen at the output after a certain latency.

The effect of asserting the SLEEP pin is seen immediately

at the output, i.e. the zero to one transition of this pin is

not sampled. However, the negative transition of SLEEP

is sampled on the internal falling edge of MCLK.

The SIGN BIT OUT Pin

The AD9834 offers a variety of outputs from the chip.

The digital outputs are available from the SIGN BIT

OUT pin. The available outputs are the comparator out-

put or the MSB of the DAC data.

This pin must be enabled before use. The enabling/dis-

abling of this pin is controlled by the bit OPBITEN (D5)

in the control register. When OPBITEN = 1, this pin is

enabled. Note that the MODE bit (D1) in the control

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