REV. 0

AD9845A

–16–

Table IV. Clamp Level Register Contents (Default Value x080)

MSB

LSB

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Clamp Level (LSB)

X

X

X

0000

0

000

0

0000

0

001

1

0000

0

010

2

•

•

•

•

•

•

1111

1110

254

1111

1111

255

Table V. Control Register Contents (Default Value x000)

Data Out

DATACLK

CLP/PBLK

SHP/SHD

PxGA

Color Steering Modes

D10 D9

D8 D7

D6

D5

D4

D3

**

D2 D1 D0

X

0 Enable

0

*

0

*

0 Rising Edge Trigger

0 Active Low 0 Active Low

0 Disable 0

0

0 Steering Disabled

1 Three-State

1 Falling Edge Trigger 1 Active High 1 Active High

1 Enable 0

0

1 Mosaic Separate

0

1

0 Interlace

0

1

1 3-Color

1

0

0 4-Color

1

0

1 VD Selected

1

1

0 Mosaic Repeat

1

1

1 User Specified

*Must be set to zero.

**When D3 = 0 (PxGA disabled) the PxGA gain is fixed to 4 dB.

Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000)

MSB

LSB

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Gain (dB)

*

XXXXX0

1

1111

+10.0

••

••

••

00

0000+4.3

11

1111+4.0

••

••

••

10

0000

–2.0

*Control Register Bit D3 must be set High (PxGA Enable) to use the PxGA Gain Registers.