AD9854SLASHPCB datasheet(23/44 Pages) AD

23 / 44 page

AD9854

–23–

REV. 0

CLR ACC2

MODE

TW1

DPW

000 (DEFAULT)

RAMP RATE

011 (CHIRP)

Figure 46. Effect of CLR ACC2 in FM Chirp Mode

HOLD

MODE

TW1

DFW

000 (DEFAULT)

RAMP RATE

011 (CHIRP)

DELTA FREQUENCY WORD

RAMP RATE

Figure 47. Illustration of HOLD Function

FM Chirp

Figure 46 graphically illustrates the effect of CLR ACC2 bit upon

the DDS output frequency. Note that reprogramming the registers

while the CLR ACC2 bit is high allows a new FTW1 frequency

and slope to be loaded.

Another function that is available only in the chirp mode is the

HOLD pin, Pin 29. This function will stop the clocking signal to

the ramp rate counter that will, in turn, halt any further clocking

pulses to the frequency accumulator, ACC1. The effect is to

halt the chirp and hold the output frequency in a static condition

at the frequency existing just before HOLD was pulled high.

When the HOLD pin is returned low, the clocks are resumed

and chirp continues. During a hold condition, user may change

the programming registers; however, the ramp rate counter must

resume operation at its previous rate until a count of zero is

obtained before a new ramp rate count can be loaded. Figure 47

illustrates the effect of the hold function on the DDS output

frequency.

Users may utilize the 32-bit automatic I/O Update counter when

constructing complex chirp or ramped FSK sequences. Since

this internal counter is synchronized with the AD9854 System

Clock, it allows precisely timed program changes to be invoked. In

this manner, user is only required to reprogram the desired

registers before the automatic I/O Update pulse is generated.

A complete discussion of this function is presented elsewhere

in this data sheet.

In the chirp mode, the destination frequency is not directly

speciﬁed. If the user fails to control the chirp, the DDS will control

itself by naturally conﬁning its output between dc and Nyquist;

however, unless terminated by the user, the chirp will continue

until power is removed.

It is the user’s choice as to what occurs when the chirp destination

frequency is reached. Here are a few of the choices:

1. Stop and hold at the destination frequency using the HOLD

pin, or by loading all zeros into the Delta Frequency Word

registers of the frequency accumulator (ACC1).

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