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ADP3604AR Arkusz danych(PDF) 7 Page - Analog Devices |
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ADP3604AR Arkusz danych(HTML) 7 Page - Analog Devices |
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7 / 8 page ![]() ADP3604 REV. 0 –7– POWER DISSIPATION The power dissipation of the ADP3604 circuit must be limited such that the junction temperature of the device does not ex- ceed the maximum junction temperature rating. Power is dissipated in two components, power loss due to volt- age drops in the switches, and the power loss due to MOSFET drive current losses. Total power dissipation is calculated: P ≈ (V IN – |VOUT|)(IOUT) + (VIN)(IS) where both VIN and VOUT are referred to ground pin of the ADP3604. For example: Assuming the worst case conditions, VIN = 5.5 V, VOUT = –2.8 V, and IOUT = 120 mA, calculated power dissipa- tion is: P ≈ (5.5 V–|–2.8 V|)(0.12) + (5.5 V)(0.003 A) = 341 mW This is far below the power dissipation capability of the ADP3604 package which is 660 mW. LAYOUT AND GROUNDING TIPS The ADP3604 switches turn on and off very fast. Good PC board layout practices will ensure the proper operation of the device. Important layout considerations include: Use adequate ground and power traces or planes. Keep components as close as possible to the device. Use short trace lengths from the input and output capacitors to the input and output pins respectively. Use single point ground for the device ground pins and the in- put and output capacitors. Improper layouts will result in poor load regulation, especially with heavy loads. APPLICATIONS ADP3604 EVALUATION BOARD LAYOUT The ADP3604 evaluation board is a general purpose circuit board. Its flexible design allows the user to optimize the circuit performance by external components selection and circuit con- figuration. The circuit board can be configured as a basic charge pump voltage inverter with one pump capacitor and two bypass capacitors or as a more complex circuit with input and output LC filters. PC layout is designed for surface mount components and can be easily configured for through hole components as well. ADP3604 8 7 3 C3 4.7µF 1 4 VIN +4.5 – +6V VOUT –3.0V C4 4.7µF 2 5 SENSE INPUT L2 10µH C5 4.7µF C2 4.7µF L1 1µH C1 4.7µF Figure 21. Evaluation Board Circuit Diagram C2 C1 C4 C5 L1 C3 L2 Figure 23. Eight-Pin SOIC-Layout, Component Placement Diagram (1 × Scale) Figure 24. Eight-Pin-SOIC Layout, Component Side (1 × Layout) Table V. Recommended Components for Circuit in Figure 21 Component Manufacturer/Type C3 Sprague, 293D475X0035D2W C1, C2, C4, C5 TOKIN, 1E475ZY5UC205F L1 Coiltronics, CTX32CT-1R0 L2 Coiltronics, CTX32CT-100 FILTERED INPUT INPUT OUTPUT FILTERED OUTPUT SHDN OUTPUT GND Figure 22. Eight-Pin SOIC Layout, Wiring Connection |
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