RT7232 datasheet(13/18 Pages) RICHTEK

13 / 18 page

RT7231/32/33/34

DS7231/32/33/34-00

March 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Output Voltage Setting

The resistive divider allows the FB pin to sense the output

voltage as shown in Figure 4.

Figure 4. Output Voltage Setting

OUT

I =

⎡⎤ ⎡

⎤

Δ× −

⎢⎥ ⎢

⎥

⎣⎦ ⎣

⎦

Having a lower ripple current reduces not only the ESR

losses in the output capacitors but also the output voltage

ripple. High frequency with small ripple current can achieve

Under Voltage Lockout Protection

The RT7231/32/33/34 has Under Voltage Lockout

Protection (UVLO) that monitors the voltage of PVCC pin.

When the VPVCC voltage is lower than UVLO threshold

voltage, the RT7231/32/33/34 will be turned off in this state.

This is non-latch protection.

Over Temperature Protection

The RT7231/32/33/34 equips an Over Temperature

Protection (OTP) circuitry to prevent overheating due to

excessive power dissipation. The OTP will shut down

switching operation when junction temperature exceeds

150

°C. Once the junction temperature cools down by

approximately 25

°C the main converter will resume

operation. To keep operating at maximum, the junction

temperature should be prevented from rising above 150

°C.

Inductor Selection

The inductor value and operating frequency determine the

ripple current according to a specific input and an output

voltage. The ripple current

ΔIL increases with higher VIN

and decreases with higher inductance.

The output voltage is set by an external resistive divider

according to the following equation. It is recommended to

use 1% tolerance or better divider resistors.

)

OUT

= 0.765 (1

×+

Input and Output Capacitors Selection

The input capacitance, CIN, is needed to filter the

trapezoidal current at the source of the high side MOSFET.

A low ESR input capacitor with larger ripple current rating

should be used for the maximum RMS current. The RMS

current is given by :

OUT

RMS

OUT(MAX)

OUT

= I

−

This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT / 2. This simple worst-case condition is

commonly used for design because even significant

deviations do not offer much relief.

Choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design. For the

input capacitor, two 10

μF and 0.1μF low ESR ceramic

capacitors are recommended.

The selection of COUT is determined by the required ESR

to minimize voltage ripple.

Moreover, the amount of bulk capacitance is also a key

for COUT selection to ensure that the control loop is stable.

The output ripple,

ΔVOUT , is determined by :

OUT

ESR

8fC

⎡⎤

Δ≤ Δ

⎢⎥

⎣⎦

The output ripple will be highest at the maximum input

voltage since

ΔIL increases with input voltage. Multiple

capacitors placed in parallel may need to meet the ESR

and RMS current handling requirements.

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

highest efficiency operation. However, it requires a large

inductor to achieve this goal. For the ripple current

selection, the value of

ΔIL = 0.2(IMAX) will be a reasonable

starting point. The largest ripple current occurs at the

highest VIN. To guarantee that the ripple current stays

below the specified maximum, the inductor value should

be chosen according to the following equation :

OUT

L(MAX)

IN(MAX)

L =

⎡⎤ ⎡

⎤

×−

⎢⎥ ⎢

⎥

×Δ

⎣⎦ ⎣

⎦

GND

VOUT

RT7231/32/33/34

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