ACTPD1M16 datasheet(6/9 Pages) AEROFLEX

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SCD3750 REV A 8/31/98

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OPERATIONS

DUAL CAS

Two CAS pins (LCAS and UCAS) are

provided to give independent control of the 16

data-I/O

pins

(I/O0-15),

with

LCAS

corresponding

I/O0-7

and

UCAS

corresponding to I/O8-15. For read or write

cycles, the column address is latched on the

first xCAS falling edge. Each xCAS going low

enables its corresponding I/Ox pin with data

associated with the column address latched

on the first falling xCAS edge. All address

setup and hold parameters are referenced to

the first falling xCAS edge. The delay time

from xCAS low to valid data out (see

parameter tCAC) is measured form each

individual xCAS to its corresponding I/Ox pin.

In order to latch in a new column address,

both xCAS pins must be brought high. The

column-precharge time (see parameter tCP )

is measured from the last xCAS rising edge to

the first xCAS falling edge of the new cycle.

Keeping

column

address

valid

while

toggling xCAS requires a minimum setup

time, tCLCH. During tCLCH at least one xCAS

must be brought low before the other xCAS is

taken high.

For early-write cycles, the data is latched on

the first xCAS falling edge. Only the I/Os that

have the corresponding xCAS low are written

into. Each xCAS must meet tCAS minimum in

order to ensure writing into the storage cell.

To latch a new address and new data, all

xCAS pins must be high and meet tCP.

PAGE MODE

Page-mode operation allows faster memory

access by keeping the same row address

while selecting random column addresses.

The time for row-address setup and hold and

address

multiplex

eliminated.

The

maximum number of columns that can be

accessed is determined by the maximum

RAS low time and the xCAS page-mode cycle

time used. With minimum xCAS page-cycle

time, all columns can be accessed without

intervening RAS cycles.

Unlike conventional page-mode DRAMs, the

column address buff-ers in this device are

activated on the falling edge of RAS. The

buffers act as transparent or flow-through

latches while xCAS is high. The falling edge of

the first xCAS latches the column addresses.

This feature allows the devices to operate at a

higher data bandwidth than conventional

page-mode

parts

because

data

retrieval

begins as soon as the column address is valid

rather than when xCAS transitions low. This

performance improvement is referred to as

enhanced

page

mode.

valid

column

address may be presented immediately after

tRAH (row-address hold time) has been

satisfied, usually well in advance of the falling

edge of xCAS. In this case, data is obtained

after tCAC maximum (access time from xCAS

low) if tAA maximum (access time from

column address) has been satisfied. In the

event that column addresses for the next page

cycle are valid at the time xCAS goes high,

minimum access time for the next cycle is

determined by tCPA (access time from rising

edge of the last xCAS).

ADDRESS: A0-9

Twenty address bits are required to decode 1

of 1048576 storage cell locations. For the

ACTPD1M16, 10 row-address bits are set up

on A0 through A9 and latched onto the chip

by RAS. Ten, column-address bits are set up

on A0 through A9 and latched onto the chip

by the first xCAS. All addresses must be

stable on or before the falling edge of RAS

and xCAS. RAS is similar to a chip enable in

that it activates the sense amplifiers as well as

the row decoder. xCAS is used as a chip

select, activating its correspond-ing output

buffer and latching the address bits into the

column-address buffers.

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