STM32F107VC datasheet(62/103 Pages) STMICROELECTRONICS

62 / 103 page

Electrical characteristics

STM32F105xx, STM32F107xx

62/104

Doc ID 15274 Rev 6

Figure 23.

Recommended NRST pin

protection

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 39. Otherwise the reset will not be taken into account by the device.

5.3.15

TIM timer characteristics

The parameters given in Table 40 are guaranteed by design.

Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM

output).

ai14132d

STM32F10x

RPU

NRST(2)

VDD

Filter

Internal reset

0.1 µF

External

reset circuit(1)

Table 40.

TIMx(1) characteristics

TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4 and TIM5 timers.

Symbol

Parameter

Conditions

Min

Max

Unit

tres(TIM)

Timer resolution time

tTIMxCLK

fTIMxCLK = 72 MHz

13.9

fEXT

Timer external clock

frequency on CH1 to CH4

fTIMxCLK/2

MHz

fTIMxCLK = 72 MHz

036

MHz

ResTIM

Timer resolution

bit

tCOUNTER

16-bit counter clock period

when internal clock is

selected

65536

tTIMxCLK

fTIMxCLK = 72 MHz 0.0139

910

µs

tMAX_COUNT Maximum possible count

65536 × 65536

tTIMxCLK

fTIMxCLK = 72 MHz

59.6

STM32F107VC Arkusz danych(PDF) 62 Page - STMicroelectronics

STM32F107VC Arkusz danych(HTML) 62 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL