VIPER28HDTR datasheet(22/32 Pages) STMICROELECTRONICS

22 / 32 page

Operation descriptions

VIPER28

22/32

Doc ID 15028 Rev 5

Equation 7

Equation 8

The RFB(DYN) is the dynamic resistance seen by the FB pin.

The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB.

The

Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be

considered instead of CFB. Using the alternative compensation network, the designer can

satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 24.

FB pin configuration (option 1)

Figure 25.

FB pin configuration (option 2)

PF B

FB DYN

()

FB1

π C

FB DYN

()

FB1

⋅

()

⋅⋅

⋅

------------------------------------------------------------------------------------------

PFB

π C

FB1

FB DYN

()

⋅

()

⋅⋅

⋅

---------------------------------------------------------------------------------------------

From sense FET

4.8V

BURST

PWM

CONTROL

Cfb

To PWM Logic

BURST-MODE

REFERENCES

BURST-MODE

LOGIC

PWM

OLP comparator

To disable logic

4.8V

From sense FET

PWM

CONTROL

PWM

BURST

To disable logic

OLP comparator

To PWM Logic

BURST-MODE

LOGIC

Cfb1

Rfb1

Cfb

BURST-MODE

REFERENCES

VIPER28HDTR Arkusz danych(PDF) 22 Page - STMicroelectronics

VIPER28HDTR Arkusz danych(HTML) 22 Page - STMicroelectronics

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