©2012 Silicon Storage Technology, Inc.

DS25024C

10/12

21

8 Mbit 1.8V SPI Serial Flash

SST25WF080

Not Recommended for New Designs

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling

any new Write operations from occurring. The WRDI instruction will not terminate any programming

WRDI instruction. CE# must be driven high before the WRDI instruction is executed. See Figure 20 for

the WRDI instruction sequence.

Figure 20:Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)

instruction and opens the status register for alteration. The Write-Status-Register instruction must be

executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-

step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP

(software data protection) command structure which prevents any accidental alteration of the status

register values. CE# must be driven low before the EWSR instruction is entered and must be driven

high before the EWSR instruction is executed. See Figure 21 for EWSR instruction followed by WRSR

instruction.

CE#

SO

SI

SCK

01 2 3 4 5 6 7

04

HIGH IMPEDANCE

MODE 0

MODE 3

1203 F19.0

MSB