MPC8280 datasheet(21/83 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

AC Electrical Characteristics

NOTE: Conditions

The following conditions must be met in order to operate the MPC8272

family devices with 133 MHz bus: single PowerQUICC II Bus mode must

be used (no external master, BCR[EBM] = 0); data bus must be in Pipeline

mode (BRx[DR] = 1); internal arbiter and memory controller must be used.

For expected load of above 40 pF, it is recommended that data and address

buses be configured to low (25

Ω) impedance (SIUMCR[HLBE0] = 1,

SIUMCR[HLBE1] = 1).

This table lists SIU output characteristics.

Table 11. AC Characteristics for SIU Inputs1

1 Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

Spec Number

Characteristic

Value (ns)

Setup

Hold

Setup

Hold

MHz

100

MHz

133

MHz

100

MHz

133

MHz

sp11

sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/TEA

3.5

N/A

0.5

N/A

sp12

sp10 Data bus in normal mode

3.5

N/A

0.5

N/A

sp13

sp10 Data bus in pipeline mode (without ECC and

PARITY)

N/A

2.5

1.5

N/A

0.5

sp15

sp10 All other pins

3.5

N/A

0.5

N/A

Table 12. AC Characteristics for SIU Outputs1

1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

Spec Number

Characteristic

Value (ns)

Max

Min

Maximum Delay

Minimum Delay

MHz

100

MHz

133

MHz

100

MHz

133

MHz

sp31

sp30

PSDVAL/TEA/TA

5.5

N/A

sp32

sp30

ADD/ADD_atr./BADDR/CI/GBL/WT

6.5

5.5

4.52

2 Value is for ADD only; other sp32/sp30 signals are not applicable.

1 2

sp33

sp30

Data bus3

3 To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.

6.5

5.5

4.5

0.8

sp34

sp30

Memory controller signals/ALE

5.5

4.5

sp35

sp30

All other signals

5.5

N/A

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