AD5204BRUZ100-R7 datasheet(9/20 Pages) AD

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AD5204/AD5206

Rev. C | Page 9 of 20

GND

VDD 6

SDI

CLK

VSS 9

B5 10

W5 11

A5 12

AD5206

TOP VIEW

(Not to Scale)

NC = NO CONNECT

Figure 8. AD5206 SOIC/TSSOP/PDIP Pin Configuration

Table 5. AD5206 Pin Function Descriptions

Pin No.

Name

Description

Terminal A RDAC 6.

Wiper RDAC 6. Address = 1012.

Terminal B RDAC 6.

GND

Ground.

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the

address bits, and then it is loaded into the target RDAC latch.

VDD

Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V.

SDI

Serial Data Input. Data is input MSB first.

CLK

Serial Clock Input. This pin is positive edge triggered.

VSS

Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |VDD| + |VSS| < 5.5 V.

Terminal B RDAC 5.

Wiper RDAC 5. Address = 1002.

Terminal A RDAC 5.

Terminal B RDAC 3.

Wiper RDAC 3. Address = 0102.

Terminal A RDAC 3.

Terminal B RDAC 1.

Wiper RDAC 1. Address = 0002.

Terminal A RDAC 1.

Terminal A RDAC 2.

Wiper RDAC 2. Address = 0012.

Terminal B RDAC 2.

Terminal A RDAC 4.

Wiper RDAC 4. Address = 0112.

Terminal B RDAC 4.

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