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ICS85320AMILF Arkusz danych(PDF) 10 Page - Integrated Device Technology

Numer części ICS85320AMILF
Szczegółowy opis  LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
PDF  16 Pages
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Producent  IDT [Integrated Device Technology]
Strona internetowa  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS85320AMILF Arkusz danych(HTML) 10 Page - Integrated Device Technology

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IDT/ ICS3.3V, 2.5V LVPECL TRANSLATOR
10
ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85320I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85320I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 25mA = 86.6mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 86.6mW + 30.2mW = 116.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.117W * 103.3°C/W = 97.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE
θθθθθ
JA
FOR
8-PIN SOIC, FORCED CONVECTION
θθθθθ
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7°C/W
103.3°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.



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