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SN74LVC841APWR Arkusz danych(PDF) 2 Page - Texas Instruments |
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SN74LVC841APWR Arkusz danych(HTML) 2 Page - Texas Instruments |
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2 / 17 page ![]() www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) OE To Nine Other Channels 1 13 2 23 LE 1D C1 1D 1Q SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS307J – MARCH 1993 – REVISED FEBRUARY 2005 OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OUTPUT Q OE LE D L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 2 |
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