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STM8AF6148 Arkusz danych(PDF) 66 Page - STMicroelectronics |
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STM8AF6148 Arkusz danych(HTML) 66 Page - STMicroelectronics |
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66 / 89 page ![]() Electrical characteristics STM8AF61xx, STM8AF62xx 66/89 Doc ID 14952 Rev 6 Figure 37. SPI timing diagram where slave mode and CPHA = 0 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 38. SPI timing diagram where slave mode and CPHA = 1 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. 4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. ai14134 CPHA= 0 MOSI INPUT MISO OUT P UT CPHA= 0 MS B O UT MSB IN BI T6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BI T1 IN NSS input tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) ai14135 CPHA=1 MOSI INPUT MISO OUT P UT CPHA=1 MS B O UT MSB IN BI T6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BI T1 IN tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) NSS input |
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