SL40307A-R19KHF datasheet(26/53 Pages) IRF

26 / 53 page

IR3846

26 www.irf.com

August 01, 2013

overrides the internal reference voltage. The external

voltage source should have a low internal resistance

(<100Ω) and be able to source and sink more than

25µA.

POWER GOOD OUTPUT (TRACKING,

SEQUENCING, VREF MARGINING)

IR3846 continually monitors the output voltage via the

sense pin (Vsns) voltage. The Vsns voltage is an input

to the window comparator with upper and lower

threshold of 1.2*VREF and 0.95*VREF respectively.

PGood signal is high whenever Vsns voltage is within

the PGood comparator window thresholds. Hysteresis

has been applied to the lower threshold, PGood signal

goes low when Vsns drops below 0.9*VREF instead

of 0.95*VREF. The PGood pin is open drain and it

needs to be externally pulled high. High state

indicates that output is in regulation.

The threshold is set differently in different operating

modes and the results of the comparison sets the

PGood signal. Figure 24, Figure 25 and Figure 26

show the timing diagram of the PGood signal at

different operating modes. Vsns signal is also used by

OVP comparator for detecting output over voltage

condition. PGood signal is low when Enable is low.

Vref

PGD

Vsns

0.6V

1.2*VREF

0.90*VREF

1.28 mS

OVP

Latch

0.95*VREF

150 uS

2.5 uS

Figure 24: Non-sequence, Non-tracking Startup

and Vref Margin (Vp pin floating)

Figure 25: Vp Tracking (Vref = 0V)

Figure 26: Vp Sequence and Vref Margin

OVER-VOLTAGE PROTECTION (OVP)

Over-voltage protection in IR3846 is achieved by

comparing sense pin voltage Vsns to a pre-set

threshold. In non-tracking mode, OVP threshold can

be set at 1.2*Vref; in tracking mode, it can be at

1.2*Vp. When Vsns exceeds the over voltage

threshold, an over voltage trip signal asserts after 2.5

uS (typ.) delay. The high side drive signal HDrv is

latched off immediately and PGood flags are set low.

The low side drive signal is kept on until the Vsns

voltage drops below the threshold.

HDrv remains

latched off until a reset is performed by cycling VCC.

OVP is active when enable is high or low.

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