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GETINFOBRIEF Arkusz danych(PDF) 27 Page - Freescale Semiconductor, Inc |
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GETINFOBRIEF Arkusz danych(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 36 page ![]() Operation MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 27 Address: $FE01 76 5 4 32 1 0 R POWER UP RESET PIN MC3PHAC FUNCTIONAL FAULT MC3PHAC FUNCTIONAL FAULT PC MASTER SOFTWARE RESET COMMAND LOW VDD VOLTAGE W Reset 1 0 0 0 0000 = Unimplemented or Reserved Figure 17. Reset Status Register Table 10. Reset Status Register Field Descriptions Field Description 7 POWER UP POWER UP Bit — This read-only bit indicates the last system reset was caused by the power-up reset detection circuit. 0 Power-up reset was not the source of the reset or a read of the reset status register after the first read. 1 The last reset was caused by an initial power-up of the MC3PHAC. 6 RESET PIN RESET PIN Bit — This read-only bit indicates the last system reset was caused from the RESET input pin. 0 The RESET pin was not the source of the reset or a read of the reset status register after the first read. 1 Last reset was caused by an external reset applied to the RESET input pin. 5–4 MC3PHAC FUNCTIONAL FAULT BITS MC3PHAC FUNCTIONAL FAULT Bits — This read-only bit indicates if the last system reset was the result of an internal system error. 0 The FUNCTIONAL FAULT was not the source of the reset or a read of the reset status register after the first read. 1 MC3PHAC internal system error PC MASTER SOFTWARE RESET COMMAND PC MASTER SOFTWARE RESET COMMAND Bit — This read-only bit indicates the last system reset was the result of a PC master software reset command. 0 The PC master software RESET COMMAND was not the source of the reset or a read of the reset status register after the first read. 1 The MC3PHAC was reset by the PC master software command reset as the result of a write of $30 to location $1000 1 LOW VDD VOLTAGE LOW VDD VOLTAGE Bit — This read-only bit indicates if the last reset was the result of low VDD applied to the MC3PHAC. 0The LOW VDD was not the source of the reset or a read of the reset status register after the first read. 1 The last reset was caused by the low power supply detection circuit. |
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