AD421BN datasheet(3/14 Pages) AD

3 / 14 page

AD421

–3–

REV. C

TIMING CHARACTERISTICS1, 2, 3

Parameter

(B Versions)

Units

Conditions/Comments

tCK

100

ns min

Data Clock Period

tCL

ns min

Data Clock Low Time

tCH

ns min

Data Clock High Time

tDW

ns min

Data Stable Width

tDS

ns min

Data Setup Time

tDH

ns min

Data Hold Time

tLD

ns min

Latch Delay Time

tLL

ns min

Latch Low Time

tLH

ns min

Latch High Time

NOTES

1Guaranteed by characterization at initial product release, not production tested.

2See Figures 1 and 2.

3All input signals are specified with tr = tf = 5 ns (10% to 90% of V

CC ) and timed from a voltage level of (VIN + VIL )/2; tr and tf should not exceed 1

µs on any digital

input.

Specifications subject to change without notice.

WORD "N"

WORD "N +1"

1 1

CLOCK

DATA

LATCH

Figure 1. Serial Interface Waveforms (Normal Data Load)

CLOCK

DATA

LATCH

Figure 2. Serial Interface Timing Diagram

(VCC = +3 V to +5 V, TA = TMIN to TMAX unless otherwise noted)

AD421BN Arkusz danych(PDF) 3 Page - Analog Devices

AD421BN Arkusz danych(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Arkusz danych Pobierz

Link URL