AD7392AR datasheet(13/20 Pages) AD

13 / 20 page

AD7392/AD7393

Rev. C | Page 13 of 20

POWER SUPPLY

The very low power consumption of the AD7392/AD7393 is

a direct result of a circuit design that optimizes the CBCMOS

process. By using the low power characteristics of CMOS for the

logic and the low noise, tight-matching of the complementary

bipolar transistors, excellent analog accuracy is achieved. One

advantage of the rail-to-rail output amplifiers used in the AD7392/

AD7393 is the wide range of usable supply voltage. The part is

fully specified and tested for operation from 2.7 V to 5.5 V.

POWER SUPPLY

RETURN

FERRITE BEAD:

2 TURNS, FAIR-RITE

#2677006301

TTL/CMOS

LOGIC

CIRCUITS

+ 100µF

ELECT.

+10µF TO 22µF

TANT.

+ 0.1µF

CER.

Figure 28. Use Separate Traces to Reduce Power Supply Noise

Whether or not a separate power supply trace is available, gen-

erous supply bypassing reduces supply line induced errors. Local

supply bypassing, consisting of a 10 μF tantalum electrolytic in

parallel with a 0.1 μF ceramic capacitor, is recommended for all

applications (see Figure 29).

VOUT

17, 18

D0 TO D11

2.7V TO 5.5V

VDD

VREF

GND

SHDN

AD7392

AD7393

0.1µF

10µF

* OPTIONAL EXTERNAL

REFERENCE BYPASS

Figure 29. Recommended Supply Bypassing for the AD7392/AD7393

INPUT LOGIC LEVELS

All digital inputs are protected with a Zener-type ESD protection

structure that allows logic input voltages to exceed the VDD supply

voltage (see Figure 30). This feature is useful if the user is driving

one or more of the digital inputs with a 5 V CMOS logic input

voltage level while operating the AD7392/AD7393 on a 3 V

power supply. If this interface is used, make sure that the VOL

of the 5 V CMOS meets the VIL input requirement of the AD7392/

AD7393 operating at 3 V. See Figure 12 for a graph of digital

logic input threshold vs. operating VDD supply voltage.

VDD

LOGIC

GND

1kΩ

Figure 30. Equivalent Digital Input ESD Protection

To minimize power dissipation from input logic levels that

are near the VIH and VIL logic input voltage specifications, a

Schmitt-trigger design was used that minimizes the input

buffer current consumption compared to traditional CMOS

input stages. Figure 11 is a plot of supply current vs. incremental

input voltage, showing that negligible current consumption

takes place when logic levels are in their quiescent state. The

normal crossover current still occurs during logic transitions.

A secondary advantage of this Schmitt trigger is the prevention

of false triggers that would occur with slow moving logic transi-

tions when a standard CMOS logic interface or opto-isolators

are used. Logic inputs D11 to D0, CS, RS, and SHDN all contain

the Schmitt-trigger circuits.

DIGITAL INTERFACE

The AD7392/AD7393 have a parallel data input. A functional

block diagram of the digital section is shown in Figure 31,

while Table 6 contains the truth table for the logic control

inputs. The chip select pin (CS) controls loading of data from

the data inputs on Pin D11 to Pin D0. This active low input

places the input register into a transparent state allowing the

data inputs to directly change the DAC ladder values. When

CS returns to logic high within the data setup-and-hold time

specifications, the new value of data in the input register are

latched. See Table 6 for a complete listing of conditions.

INTERNAL

DAC SWITCHES

1 OF 12 LATCHES

OF THE

DAC REGISTER

Figure 31. Digital Control Logic

Table 6. Control Logic Truth Table

DAC Register Function

Latched

Transparent

↑1

Latched with new data

Loaded with all zeros

↑1

Latched all zeros

↑ = Positive logic transition.

2 X = Don’t care.

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