| Zakładka z wyszukiwarką danych komponentów |
|
MCP111 Arkusz danych(PDF) 13 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MCP111 Arkusz danych(HTML) 13 Page - Microchip Technology |
|
13 / 28 page ![]() 2004-2013 Microchip Technology Inc. DS21906C-page 13 MCP102/103/121/131 4.2 Negative Going VDD Transients The minimum pulse width (time) required to cause a reset may be an important criteria in the implementa- tion of a Power-on Reset (POR) circuit. This time is referred to as transient duration, defined as the amount of time needed for these supervisory devices to respond to a drop in VDD. The transient duration time is dependant on the magnitude of VTRIP – VDD. Generally speaking, the transient duration decreases with increases in VTRIP – VDD. Figure 4-3 shows a typical transient duration vs. reset comparator overdrive, for which the MCP102/103/121/131 will not generate a reset pulse. It shows that the farther below the trip point the transient pulse goes, the duration of the pulse required to cause a reset gets shorter. Figure 2-32 shows the transient response characteristics for the MCP102/103/121/131. A 0.1 µF bypass capacitor, mounted as close as possible to the VDD pin, provides additional transient immunity (refer to Figure 4-1). FIGURE 4-3: Example of Typical Transient Duration Waveform. 4.3 Reset Power-up Timer (tRPU) Figure 4-4 illustrates the device current states. While the system is powering down, the device has a low current. This current is dependent on the device VDD and trip point. When the device VDD rises through the voltage trip point (VTRIP), an internal timer starts. This timer consumes additional current until the RST pin is driven (or released) high. This time is known as the Reset Power-up Time (tRPU). Figure 4-4 shows when tRPU is active (device consuming additional current). FIGURE 4-4: Reset Power-up Timer Waveform. 4.3.1 EFFECT OF TEMPERATURE ON RESET POWER-UP TIMER (TRPU) The Reset Power-up timer time-out period (t RPU) determines how long the device remains in the reset condition. This is affected by both VDD and temperature. Typical responses for different VDD values and temperatures are shown in Figures 2-26, 2-27 and 2-28. Time (µs) 0V 5V VTRIP(MIN) - VDD tTRANS VTRIP(MAX) VTRIP(MIN) VTRIP VDD RST tRPU Reset Power-up Timer Inactive Reset Power-up Timer Inactive See Figures 2-1, 2-2 and 2-3 See Figures 2-4, 2-5 and 2-6 See Figures 2-1, 2-2 and 2-3 |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |