LSM6DB0TR datasheet(36/66 Pages) STMICROELECTRONICS

Numer części	LSM6DB0TR

Szczegółowy opis	3D accelerometer, 3D gyroscope and signal processor

PDF	66 Pages

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Producent	STMICROELECTRONICS [STMicroelectronics]

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Microprocessor functionality

LSM6DB0

36/66

DocID025603 Rev 1

8.13

JTAG and SW debug support

The ARM JTAG debug port is embedded which enables debug using a standard JTAG

connection. The ARM serial wire debug port is also embedded which enables serial wire

debug to be connected to the CPU. The JTAG TMS and TCK pins are shared with the

SW_TDIO and SW_TCK respectively.

There are two mechanisms to select the debug mode. JTAG debug mode is selected by

setting the IO9 pin to zero. During reset, the SW debug mode is selected by default.

Figure 16. Debug mode selection timing

1. RESETN needs an external pull-up if not driven

1. Default option depending on software configuration

Table 14. Debug mode selection

POR

IO9

Debug mode

JTAG: SOC(1) + CPU TAP(2) selected

1. SOC = chip and processor

2. TAP = test access port

SW: CPU TAP(2) selected

1X(3)

3. X = don’t care

JTAG or SW available

LSM6DB0TR Arkusz danych(PDF) 36 Page - STMicroelectronics