ADM1275-2ARQZ-R7 datasheet(13/48 Pages) AD

13 / 48 page

Data Sheet

ADM1275

Rev. D | Page 13 of 48

Pin No.

QSOP

LFCSP

Mnemonic

Description

VOUT

This pin is used to read back the output voltage using the internal ADC. A 1 kΩ resistor should be

inserted in series between the source of a FET and the VOUT pin.

GND

Chip Ground Pin.

GATE

Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven

by the FET drive controller, which uses a charge pump to provide a pull-up current to charge the FET

gate pin. The FET drive controller regulates to a maximum load current by regulating the GATE pin.

GATE is held low when the supply is below UVLO.

SENSE−

Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets

the analog current limit. The hot-swap operation of the ADM1275 controls the external FET gate to

maintain the sense voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin.

SENSE+

Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor

between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation

of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This

pin is also used to measure the supply input voltage using the ADC.

N/A

EPAD

Exposed Paddle on Underside of LFCSP. Solder the exposed paddle to the board to improve thermal

dissipation. The exposed paddle can be connected to ground.

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