AM79C989 datasheet(13/37 Pages) AMD

13 / 37 page

Am79C989

PRELIMINARY

FUNCTIONAL DESCRIPTION

Overview

The QuEST device is a highly integrated physical layer

solution for twisted pair 10-Mbps Ethernet applications.

There are three main sets of interfaces to the QuEST.

On the network side, there are the 10BASE-T transmit

and receive interfaces and one Attachment Unit Inter-

face (AUI). On the system side, there are the QuASI In-

terface and the Management Interface.

The QuEST device supports four independent ports,

each consisting of a 10BASE-T transceiver with

on-chip ﬁltering and a Manchester encode/decode unit.

The QuEST device incorporates transmit drivers which

shape the Manchester waveform and facilitate ﬁlterless

operation.

The QuEST device provides the option of implementing

an AUI suitable for coaxial and ﬁber MAUs. When the

AUI is used, 10BASE-T port 0 is disabled. Ports 1, 2,

and 3 remain for 10BASE-T use.

Each 10BASE-T channel is composed of these main

circuits: 10BASE-T driver, 10BASE-T receiver, Link In-

tegrity with Auto-Negotiation, Manchester Encoding,

Manchester Decoding, and Elasticity FIFO. Shared

circuits are the following: the QuASI Interface and the

Management Interface with Conﬁguration and Status

Registers.

The QuEST device supports Auto-Negotiation as de-

ﬁned by the IEEE 802.3u standard. If the two pieces of

networking equipment at each end of a physical link are

both capable of Auto-Negotiation, they can exchange

information about their respective capabilities and po-

tentially agree to move to a different mode of operation.

In the case of the QuEST device, the primary capability

it can advertise is full-duplex operation, offering the po-

tential of a 20-Mbps link instead of 10 Mbps. The

QuEST device also supports “Next Page,” offering the

ﬂexibility to add new features in the future.

The QuASI is a unique feature of the QuEST device.

This serial interface multiplexes the data for all four se-

rial channels onto one set of pins similar to AMD’s Gen-

eral Purpose Serial Interface (GPSI). This interface

runs at 40 MHz, providing a data rate for these pins four

times faster than a standard 10-Mbps serial interface.

This approach reduces the pin count and size of the

QuEST device, as well as substantially reducing the

number of pins needed to interface the QuEST device

to the switching device.

The QuEST device has a 2-pin Management Interface,

controlled by the system switch, which allows the

QuEST device to be polled for status information. This

interface supports the MII protocols speciﬁed in the

IEEE 802.3u standard. Of the two pins, MDC is the

management clock and MDIO is the bidirectional data

and control signal.

To further optimize operation, the QuEST device has

been designed so that an interrupt mode can be se-

lected to reduce delay associated with polling the sta-

tus registers.

The QuEST device is designed to easily and reliably in-

terface to systems using either 3.3 V or 5 V supplies.

This is accomplished by having a separate power sup-

ply pin, VDDIO, which can be connected to either a 3.3

V or a 5 V supply. The digital interface pins of the QuASI

interface and the Management Interface are the only

pins affected by the choice of supply.

10BASE-T Interface

The 10BASE-T interface section is composed of sev-

eral circuits and logic blocks: 10BASE-T transmitter,

10BASE-T receiver, Collision, and Link Integrity with

Auto-Negotiation. The QuEST device contains four

identical 10BASE-T circuits.

10BASE-T Transmitter

The 10BASE-T transmitter is composed of several im-

portant sub circuits. The major function of the 10BASE-

T driver is to impart an analog waveform in Manchester

format which adheres to the IEEE 802.3i 10BASE-T

speciﬁcation. The transmitter consists of a 10BASE-T

driver with on-chip ﬁltering, Jabber timer, and provi-

sions to generate Link pulses for Link Integrity and

Auto-Negotiation functions.

Driver

The QuEST device incorporates a waveform driver,

eliminating the need for off-chip ﬁlters. The driver circuit

requires a 5 V supply. The 10BASE-T driver circuit

shapes the analog waveform in a pre-distorted manner,

emulating the effect of an external ﬁlter. The transmitter

requires a 110-

Ω (1% tolerance) resistor connected in

parallel with the TXD pins. The waveform generated is

compliant with the IEEE 802.3i Ethernet speciﬁcation.

During idle periods, 10BASE-T driver pins ﬂoat to a

high impedance state at mid-supply voltage. During

idle periods, power consumption is minimized.

Jabber Condition

The 10BASE-T transmit circuit includes a Jabber timer

which prevents the transmission of an excessively long

frame. The Jabber condition is invoked when a frame

longer than 30 ms is transmitted from the QuASI inter-

face to the 10BASE-T driver. When the Jabber condi-

tion is invoked, the transmit enable must be held

inactive for approximately 0.5 seconds to allow the Jab-

ber condition to reset. The Jabber timer provides a sim-

ple method to protect the network from excessively

long frames. When the Jabber condition is invoked, the

Collision indication will be asserted if the Link Integrity

state machine is in the pass state.

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