W25Q80BWSVIP datasheet(28/74 Pages) WINBOND

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W25Q80BW

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7.2.13

Fast Read Quad Output (6Bh)

The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction

except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be

executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE

must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the

W25Q80BW at four times the rate of standard SPI devices.

The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC

Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address

as shown in figure 12. The dummy clocks allow the device's internal circuits additional time for setting up

the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should

be high-impedance prior to the falling edge of the first data out clock.

/CS

CLK

Mode 0

Mode 3

Instruction (6Bh)

High Impedance

24-Bit Address

/CS

CLK

Dummy Clocks

High Impedance

Byte 1

High Impedance

Byte 2

Byte 3

Byte 4

0 switches from

Input to Output

= MSB

Figure 12. Fast Read Quad Output Instruction Sequence Diagram

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