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STM8S103F2U6TR Arkusz danych(PDF) 80 Page - STMicroelectronics |
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STM8S103F2U6TR Arkusz danych(HTML) 80 Page - STMicroelectronics |
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80 / 113 page ![]() Table 43: SPI characteristics Unit Max Min Conditions (1) Parameter Symbol MHz 8 0 Master mode SPI clock frequency fSCK1/ tc(SCK) MHz 7 (2) 0 SPI clock frequency fSCK1/ tc(SCK) fSCK1/ tc(SCK) ns 25 Capacitive load: C = 30 pF SPI clock rise and fall time tr(SCK) tf(SCK) 4 x tMASTER Slave mode NSS setup time tsu(NSS) (3) 70 Slave mode NSS hold time th(NSS) (3) tSCK/ 2 +15 tSCK/ 2 - 15 Master mode SCK high and low time tw(SCKH) (3) tw(SCKL) (3) 5 Master mode Data input setup time tsu(MI) (3) tsu(SI) (3) 5 Slave mode 7 Master mode Data input hold time th(MI) (3) th(SI) (3) 10 Slave mode 3 x tMASTER Slave mode Data output access time ta(SO) (3) (4) 25 Slave mode Data output disable time tdis(SO) (3) (5) 65 (2) Slave mode (after enable edge) Data output valid time tv(SO) (3) 30 Master mode (after enable edge) Data output valid time tv(MO) (3) 27 (2) Slave mode (after enable edge) Data output hold time th(SO) (3) 11 (2) Master mode (after enable edge) Data output hold time th(MO) (3) DocID15441 Rev 6 80/113 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics |
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