STM32F415RG datasheet(156/186 Pages) STMICROELECTRONICS

156 / 186 page

Electrical characteristics

STM32F415xx, STM32F417xx

156/186

DocID022063 Rev 4

5.3.26

Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from

tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage

summarized in Table 13, with the following configuration:

•

PCK polarity: falling

•

VSYNC and HSYNC polarity: high

•

Data format: 14 bits

Figure 73. DCMI timing diagram

Table 86. Switching characteristics for NAND Flash write cycles(1)

1. CL = 30 pF.

Symbol

Parameter

Min

Max

Unit

tw(NWE)

FSMC_NWE low width

4THCLK–1

4THCLK+ 3

tv(NWE-D)

FSMC_NWE low to FSMC_D[15-0] valid

th(NWE-D)

FSMC_NWE high to FSMC_D[15-0] invalid

3THCLK –2

td(D-NWE)

FSMC_D[15-0] valid before FSMC_NWE high

5THCLK–3

td(ALE-NWE)

FSMC_ALE valid before FSMC_NWE low

3THCLK

th(NWE-ALE)

FSMC_NWE high to FSMC_ALE invalid

3THCLK–2

Table 87. DCMI characteristics(1)

Symbol

ParameterMin

Max

Unit

Frequency ratio DCMI_PIXCLK/fHCLK

-0.4

DCMI_PIXCLK

Pixel clock input

MHz

Dpixel

Pixel clock input duty cycle

MS32414V1

Pixel clock

tsu(VSYNC)

tsu(HSYNC)

HSYNC

VSYNC

DATA[0:13]

1/DCMI_PIXCLK

th(HSYNC)

tsu(DATA) th(DATA)

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