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Datasheet - Detailed Descr i pti on

8.2 Watchdog Input

The integrated watchdog feature can be used to monitor processor activity via pin WDI, and can detect pulses as short as 50ns. The watchdog

requires that the processor toggle the watchdog logic input at regular intervals, within a specified minimum timeout period (1.5s, typ). A reset is

asserted for the reset timeout period. As long as reset is asserted, the timer remains cleared and is not incremented. When reset is deasserted,

the watchdog timer starts counting (Figure 11).

Note:

The watchdog timer can be cleared with a reset pulse or by toggling WDI.

Figure 11. Watchdog Timing Relationship

watchdog timeout period. When pin WDI is left unconnected, this internal driver clears the watchdog timer every 1.4s. When WDI is tri-stated or

is not connected, the maximum allowable leakage current is 10µA and the maximum allowable load capacitance is 200pF.

Note:

The watchdog function can be disabled by leaving pin WDI unconnected or connecting it to a tri-state output buffer.

8.3 Manual Reset Input

The active-low pin MRN is used to force a manual reset. This input can be driven by CMOS logic levels or with open-drain collector outputs.

MRN goes high (140ms min). The manual reset circuitry has an internal 50k

Ω pullup resistor, thus it can be left open if not used.

To create a manual-reset circuit, connect a normally open momentary switch from pin MRN to GND (see Figure 1 on page 1); external debounce

circuitry is not required in this configuration.

If MRN is driven via long cables or the device is used in a noisy environment, a 0.1µF capacitor between pin MRN and GND will provide

additional noise immunity.

The RESET signal is the inverse of the RESETN signal.

VCC

RESETN

WDI